The present invention relates to semiconductor devices which include, between the major surfaces thereof, a layer with low electrical resistance and an alternating conductivity type layer formed of regions of a first conductivity type and regions of a second conductivity type alternately arranged with each other. Specifically, the present invention relates to vertical semiconductor devices, which facilitate the realization of a high breakdown voltage and a high current capacity, such as MOSFET""s (insulated gate field effect transistors), IGBT""s (conductivity-modulation-type MOSFET""s), bipolar transistors and diodes. The present invention relates also to the method of manufacturing the semiconductor devices described above.
The semiconductor devices may be roughly classified into lateral semiconductor devices arranged with electrodes on a major surface, and vertical semiconductor devices which distribute electrodes on both major surfaces facing opposite to each other. When the vertical semiconductor device is ON, a drift current flows in the thickness direction of the semiconductor chip (vertical direction). When the vertical semiconductor device is OFF, the depletion layers caused by applying a reverse bias voltage also expands in the vertical direction.
FIG. 7 is a cross sectional view of a conventional planar-type n-channel vertical MOSFET. Referring now to FIG. 7, the vertical MOSFET includes an n+-type drain layer 11 with low electrical resistance, a drain electrode 18 in electrical contact with n+-type drain layer 11, a highly resistive nxe2x88x92-type drift layer 12 on n+-type drain layer 11, p-type base regions 13 formed selectively in the surface portion of nxe2x88x92-type drift layer 12, a heavily doped n+-type source region 14 formed selectively in p-type base region 13, a gate insulation film 15 on the extended portion of p-type base region 13 extended between n+-type source region 14 and nxe2x88x92-type drift layer 12, a gate electrode layer 16 on gate insulation film 15, and a source electrode 17 in electrical contact commonly with n+-type source regions 14 and p-type base region 13, and a drain electrode 18 on the back surface of n+-type drain layer 11.
In the vertical semiconductor device shown in FIG. 7, highly resistive nxe2x88x92-type drift layer 12 works as a region for making a drift current flow vertically when the MOSFET is in the ON-state. In the OFF-state of the MOSFET, n-type drift layer 12 is depleted, causing a high breakdown voltage. Thinning highly resistive nxe2x88x92-type drift layer 12, that is shortening the drift current path, is effective for substantially reducing the on-resistance (resistance between the drain and the source) of the MOSFET, since the drift resistance is lowered in the ON-state of the device. However, since the space between the drain and the source, into that the depletion layers expand from the pn-junctions between p-type base regions 13 and nxe2x88x92-type drift layer 12 in the OFF-state of the device, is narrowed by shortening the drift current path in nxe2x88x92-type drift layer 12, the electric field strength in the depletion layers soon reaches the maximum (critical) value for silicon. Therefore, breakdown is caused before the voltage between the drain and the source reaches the designed breakdown voltage of the device.
A high breakdown voltage is obtained by thickening nxe2x88x92-type drift layer 12. However, a thick nxe2x88x92-type drift layer 12 inevitably causes high on-resistance and loss increase. In short, there exists a tradeoff relation between the on-resistance (current capacity) and the breakdown voltage of the MOSFET.
The tradeoff relation exists in the other semiconductor devices, such as IGBT""s, bipolar transistors and diodes. The tradeoff relation exists also in the lateral semiconductor devices, therein the flow direction of the drift current in the ON-state of the devices is different from the expansion direction of the depletion layers in the OFF-state of the devices.
European Patent 0 053 854, U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215, and Japanese Unexamined Laid Open Patent Application H09(1997)-266311 disclose semiconductor devices, which reduce the tradeoff relation described above by employing an alternating-conductivity-type drift layer formed of heavily doped n-type regions and p-type regions alternately laminated horizontally with each other.
FIG. 8 is a cross sectional view of the vertical MOSFET disclosed in U.S. Pat. No. 5,216,275. Referring now to FIG. 8, the vertical MOSFET of FIG. 8 is different from the vertical MOSFET of FIG. 7 in that the vertical MOSFET of FIG. 8 includes an alternating conductivity type drift layer 22 that is not a single-layered one but formed of n-type drift regions 22a and p-type partition regions 22b alternately laminated horizontally with each other. In FIG. 8, p-type base regions 23, n+-type source regions 24, gate insulation film 25, gate electrodes 26, a source electrode 27, and a drain electrode 28 are also shown.
Drift layer 22 is formed in the following way. A highly resistive n-type layer is formed epitaxially on n+-type drain layer 21 as a substrate. Trenches are dug selectively in the n-type layer down to n+-type drain layer 21 by etching, leaving n-type drift regions 22a. Then, p-type partition regions 22b are formed by epitaxially growing p-type layers in the trenches.
The alternating conductivity type layer provides a drift current path in the ON-state of the device and is depleted in the OFF-state of the device. Hereinafter, the semiconductor device including an alternating conductivity type drift layer will be referred to as the xe2x80x9csuper-junction semiconductor devicexe2x80x9d.
The dimensions and the impurity concentrations of the constituent elements in the super-junction semiconductor device described in U.S. Pat. No. 5,216,275 are as follows. Assuming that the breakdown voltage is VB, drift layer 22 is 0.024 VB1.2 (xcexcm) in thickness, and n-type drift region 22a and p-type partition region 22b have the same width b and the same impurity concentration, the impurity concentrations in n-type drift region 22a and p-type partition region 22b are expressed by 7.2xc3x971016VBxe2x88x920.2/b(cmxe2x88x923). When VB=800 V and b=5 xcexcm, drift layer 22 is 73 xcexcm in thickness and the impurity concentration thereof is 1.9xc3x971016 cmxe2x88x923. Obviously, the alternating conductivity type drift layer reduces the on-resistance, since the impurity concentration in the single-layered drift layer is around 2xc3x971014 cm-3. However, it is very difficult for the epitaxial growth technique available at present to bury semiconductor layers with a good quality in such narrow and deep trenches, that is trenches with a large aspect ratio.
As described above, the tradeoff relation between the on-resistance and the breakdown voltage poses a problem also on the lateral semiconductor devices. European Patent 0 053 854, U.S. Pat. No. 5,438,215, and Japanese Unexamined Laid Open Patent Application H09(1997)-266311 disclose also lateral super-junction semiconductor devices and the methods of manufacturing the lateral super-junction semiconductor devices. The disclosed methods employ selective etching to dig trenches and epitaxial growth to bury the trenches. It is not so difficult for the selective etching technique and the epitaxial growth technique to form the alternating-conductivity-type drift layer for the lateral super-junction semiconductor device, since the lateral alternating-conductivity-type drift layer is formed by laminating thin epitaxial layers vertically.
However, the conventional selective etching and epitaxial growth techniques are not so effective to form the vertical alternating-conductivity-type drift layer described in U.S. Pat. No. 5,216,275. Japanese Unexamined Laid Open Patent Application H09(1997)-266311 describes a nuclear transformation technique that uses a neutron beam and such a radioactive ray for forming n-type regions and p-type regions in the alternating-conductivity-type drift layer. However, it is not so easy to apply the nuclear transformation technique which employs large facilities.
For reducing the chip size of the conventional super-junction semiconductor device, it is necessary to reduce the dimensions of the constituent layers and regions constituting the surface semiconductor structure of the device. The reduced dimensions inevitably lower the mass-productivity of the device. Change of the surface structure causes additional manufacturing costs.
In view of the foregoing, it would be desirable to provide a super-junction semiconductor device that facilitates reducing the tradeoff relation between the on-resistance and the breakdown voltage, obtaining a high breakdown voltage and reducing the on-resistance to increase the current capacity. It would further be desirable to provide the method for manufacturing a super-junction semiconductor device easily with excellent mass-productivity.
According to an aspect of the invention, there is provided a semiconductor device including: a semiconductor chip having a first major surface and a second major surface facing in opposite to the first major surface; a layer with low electrical resistance on the side of the second major surface; a first alternating conductivity type layer above the layer with low electrical resistance, the first alternating conductivity type layer including one or more first regions of a first conductivity type and second regions of a second conductivity type, the one or more first regions and the second regions forming first pn-junctions therebetween; and a second alternating conductivity type layer in plane contact with the first alternating conductivity type layer, the second alternating conductivity type layer including one or more third regions of the first conductivity type and fourth regions of the second conductivity type, the one or more third regions and the fourth regions forming second pn-junctions therebetween; the second pn-junctions in the second alternating conductivity type layer being spaced apart from each other more widely than the first pn-junctions in the first alternating conductivity type layer.
Advantageously, the boundary between the first alternating conductivity type layer and the second alternating conductivity type layer extends almost in parallel to the first major surface.
Advantageously, the second alternating conductivity type layer is between the first alternating conductivity type layer and the first major surface.
Advantageously, the surfaces of the first pn-junctions in the first alternating conductivity type layer are almost perpendicular to surfaces of the second pn-junctions in the second alternating conductivity type layer.
Advantageously, the one or more first regions of the first conductivity type in the first alternating conductivity type layer are connected to the one or more third regions of the first conductivity type in the second alternating conductivity type layer, and the second regions of the second conductivity type in the first alternating conductivity type layer are connected to the fourth regions of the second conductivity type in the second alternating conductivity type layer.
Advantageously, the one or more third regions and the fourth regions in second alternating conductivity type layer are arranged differently from the one or more first regions and the second regions in first alternating conductivity type layer.
The super-junction semiconductor device according to the invention, in that the spacing between the second pn-junctions in the second alternating conductivity type layer is wider than the spacing between the first pn-junctions in the first alternating conductivity type layer, facilitates reducing the on-resistance without condensing the surface structure of the semiconductor chip and, therefore, without increasing the manufacturing costs. Even when the boundary between the first alternating conductivity type layer and the second alternating conductivity type layer extends in perpendicular to the first major surface, the on-resistance is reduced without condensing the surface structure of the semiconductor chip. Since the super-junction semiconductor device according to the invention reduces the on-resistance simply by narrowing the spacing between the pn-junctions in the alternating conductivity type layer inside the semiconductor chip, the costs of mass-producing the super-junction semiconductor device are reduced.
According to another aspect of the invention, there is provided the method of manufacturing a semiconductor device including a semiconductor chip having a first major surface and a second major surface facing in opposite to the first major surface; a layer with low electrical resistance on the side of the second major surface; a first alternating conductivity type layer above the layer with low electrical resistance, the first alternating conductivity type layer being formed of one or more first regions of a first conductivity type and second regions of a second conductivity type, the one or more first regions and the second regions forming first pn-junctions therebetween; and a second alternating conductivity type layer in plane contact with the first alternating conductivity type layer, the second alternating conductivity type layer being formed of one or more third regions of the first conductivity type and fourth regions of the second conductivity type, the one or more third regions and the fourth regions forming second pn-junctions therebetween; the second pn-junctions in the second alternating conductivity type layer being spaced apart from each other more widely than the first pn-junctions in the first alternating conductivity type layer, the method including the steps of: (a) forming an epitaxial layer; (b) implanting an impurity of the second conductivity type selectively into first surface portions of the epitaxial layer; (c) implanting an impurity of the first conductivity type selectively into second surface portions of the epitaxial layer; (d) repeating the steps (a) through (c) as many times as necessary; and (e) thermally driving all the implanted impurities, whereby to form the first alternating conductivity type layer and the second alternating conductivity type layer. Preferably, the steps (a) through (c) are repeated three times or more.
The method of manufacturing the super-junction semiconductor device according to the invention facilitates changing the spacing between the pn-junctions in the second alternating conductivity type layer on the side of the first major surface form the spacing between the pn-junctions in the first alternating conductivity type layer on the side of the second major surface. In other words, the method of manufacturing the super-junction semiconductor device according to the invention facilitates reducing the on-resistance simply by narrowing the spacing between the pn-junctions in the alternating conductivity type layer inside the semiconductor chip. Therefore, the method of manufacturing the super-junction semiconductor device according to the invention is effective to reduce the costs of mass-producing the super-junction semiconductor devices.